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STDVE103A
Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer
Preliminary Data
Features

Digital video signal equalizer with 3:1 HDMI switch Compatible with the high-definition multimedia interface (HDMI) v1.3 digital interface 340 MHz maximum clock speed operation supports all video formats with deep color at maximum refresh rates 3.4 Gbps data rate per channel Fully automatic adaptive equalizer for cable lengths up to 25 m Selectable 50 input termination to VCC: 3.135 to 3.465 V Low speed control lines supply to VDD : 5 V (typ) ESD HBM model : > 5 KV for all I/Os Integrated open-drain I2C buffer for display data channel (DDC) 5.3 V tolerant DDC and HPD I/Os Lock-up free operation of I2C bus 0 to 400 kHz clock frequency for I2C bus Low capacitance TMDS channels Equalizer for signal regeneration Low output skew and jitter
TQFP64

Description
The STDVE103A integrates a 4-channel 3.4 Gbps TMDS equalizer and a 3:1 switch to select one of the three HDMI ports. The high-speed data paths and flow-through pinout minimize the internal device jitter and simplify the board layout. The equalizer overcomes the jitter effects from lossy cables. The buffer/driver on the output can drive the TMDS output signals over long distances. Also, STDVE103A integrates the 50 W termination resistor on all the input channels to improve performance and reduce board space. The device can be placed in a low-power mode by disabling the output current drivers. The differential signal from the HDMI/DVI ports can be routed through the STDVE103A to guarantee good signal quality at the HDMI receiver. Designed for very low skew, jitter and low I/O capacitance, the switch preserves the signal integrity to pass the stringent HDMI compliance requirements.
Applications

Advanced TVs supporting the HDMI/DVI standard Front projectors, LCD TVs and PDPs Monitors and notebooks Set-top box and DVD players Device summary
Operating temperature -40C to 85C
Table 1.
Order code STDVE103A
Package TQFP64
Packaging Tape and reel
July 2008
Rev 1
1/43
www.st.com 43
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STDVE103A
Contents
1 2 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.1 SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-down condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 5.2 5.3 5.4 5.5 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC electrical characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . . . . . 24 Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Dynamic switching characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . 28
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1 6.2 6.3 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.1 I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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STDVE103A
Contents
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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List of tables
STDVE103A
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Gain frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC specifications for TMDS differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC specifications for TMDS differential ouputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC specifications for SEL (S1, S2) inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input termination resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 External reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DDC I/O pins (switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Status pins (HPD_SINK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Status pins (HPD1, HPD2, HPD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Input/output SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Equalizer gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Status pins (HPD_SINK, HPD1, HPD2, HPD3, S1, S2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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STDVE103A
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. STDVE103A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Equalizer functional diagram (one signal pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DDC I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 STDVE103A in a digital TV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin configuration (TQFP64 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STDVE103A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TMDS output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Test circuit for turn off and turn off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Test circuit for short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 TSK(O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSK(D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC waveform 1 (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Test circuit for AC measurements (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 I2C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical application of I2C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TQFP64 tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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General description
STDVE103A
1
General description
The STDVE103A is a TMDS/HDMI 3:1 switch with signal equalizer. The device is a HDMI switch featuring an integrated 4-channel 3.4 Gbps TMDS equalizer and 3:1 switch to select one of the three HDMI ports (either external ports or internal sources). The high-speed data paths and flow-through pinout minimize the internal device jitter and simplify the board layout. The equalizer provides compensation to overcome the intersymbol interference (ISI) jitter effects from lossy cables. The output driver buffers the TMDS output signals over long distances. Also, the STDVE103A integrates the 50 termination resistor on all the input channels to improve performance and reduce board space. The device can operate in a low-power mode by disabling the output current drivers. The STDVE103A is ideal for advanced TV and STB applications supporting the HDMI/DVI standard. The differential signal from the HDMI/DVI ports can be routed through the STDVE103A to guarantee good signal quality at the HDMI receiver. Designed for very low skew, jitter and low I/O capacitance, the switch preserves the signal integrity to pass the stringent HDMI compliance requirements. The STDVE103A provides the ability to boost the incoming TMDS signal and drive it to a level which allows efficient signal recovery at the HDMI receiver. It is especially useful for boosting signals for longer distance transmission when the HDMI receiver is physically distant from the HDMI input port.
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STDVE103A
Block diagram
2
Block diagram
Figure 1. STDVE103A block diagram
HDMI input port A HDMI input port B HDMI input port C
2
3:1 HDMI input select switch
Input stage
Equalizer
Output driver/ transmitter
HDMI output port Y
DDC port A DDC port B DDC port C S1,S2 HPD port A HPD port B HPD port C
2 2
DDC switch
2
IC repeater
2
DDC port Y
HPD analog switch
HPD port Y
CS00061A
Figure 2.
Equalizer functional diagram (one signal pair)
S1, S2
Data+ 50 termination Data- selectable Pre-Amp
Quantizer
Data+ Switch (3:1) Equalizer
Output I driver
Data-
S1,S2 REXT
Current control
AM00716V1
7/43
Block diagram Figure 3. DDC I2C bus repeater
I2C Bus Repeater
STDVE103A
A_DDC_SDA B_DDC_SDA C_DDC_SDA Switch A_DDC_SCL B_DDC_SCL C_DDC_SCL
Y_DDC_SDA
Y_DDC_SCL
S1, S2
2.1
Application diagrams
Figure 4. STDVE103A in a digital TV
Game console Digital TV
DVD-R
STB
STDVE103A
HDMI receiver
CS00063A
8/43
STDVE103A
Pin configuration
3
Pin configuration
Figure 5. Pin configuration (TQFP64 package)
HPD3 SCL2 HPD2 50 SDA2 GND VCC A24 B23 A22 B22 VCC B24 A23 A21 B21 VDD 49
61
60
62
59
63
57
54
56
58
55
64
53
52
51
48 47 46 45 44 43 42 41
A14 B14 VCC A13 B13 GND A12 B12 VCC A11 B11 SCL 1 SDA 1 HPD 1 NC S2
SDA 3 SCL 3 GND B31 A31 VCC B32 A32 GND B33 A33 VCC B 34 A34 GND REXT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 STDVE103A
40 39 38 37 36 35 34 33
18
20
21
19
24
26
23
27
17
22
25
Z1
28
SCL_SINK
29
Y1
SDA_SINK
GND
GND
VCC
Table 2.
Pin number 1-2 3 4-5 6 7-8 9 10-11
Pin description
Pin name SDA3, SCL3 GND B31, A31 Type I/O Power Input, TMDS Power Input, TMDS Power Input, TMDS Power Input, TMDS Power Function Port3 DDC bus data and clock lines Ground Port 3 differential inputs for channel 1 Supply voltage (3.3 V 5%) Port 3 differential inputs for channel 2 Ground Port 3 differential inputs for channel 3 Supply voltage (3.3 V 5%) Port 3 differential inputs for channel 4 Ground
VCC
B32, A32 GND B33, A33 VCC B34, A34 GND
12 13-14 15
HPD_SINK
Y4
VCC
Z3
Y2
Y3
Z2
Z4
S1
32
30
31
16
9/43
Pin configuration Table 2.
Pin number 16
STDVE103A Pin description (continued)
Pin name REXT Type Analog Output, TMDS Power Output, TMDS Power Output, TMDS Power Output, TMDS Power I/O I/O Function Connect to GND through a 4.7 K 1% precision reference resistor. Sets the output current to generate the output voltage compliant with TMDS Channel 4 differential outputs Supply voltage (3.3 V 5%) Channel 3 differential outputs Ground Channel 2 differential outputs Supply voltage (3.3 V 5%) Channel 1 differential outputs Ground Sink side DDC bus clock line Sink side DDC bus data line Sink side hot plug detector input High: 5 V power signal asserted from source to sink and EDID is ready Low: No 5 V power signal is asserted from source to sink or EDID is not ready Source select inputs No connect Output I/O I/O Input, TMDS Power Input, TMDS Power Input, TMDS Power Input, TMDS Power Output I/O Port 1 hot plug detector output. Port 1 DDC bus data line Port 1 DDC bus clock line Port 1 differential inputs for channel 1 Supply voltage (3.3 V 5%) Port 1 differential inputs for channel 2 Ground Port 1 differential inputs for channel 3 Supply voltage (3.3 V 5%) Port 1 differential inputs for channel 4 Supply voltage (5.0 V 10%) for DDC, HPD and source selector pins Port 2 hot plug detector output Port 2 DDC bus data line
17-18 19 20-21 22 23-24 25 26-27 28 29 30
Y4, Z4
VCC
Y3, Z3 GND Y2, Z2
VCC
Y1, Z1 GND SCL_SINK SDA_SINK
31
HPD_SINK
Input
32-33 34 35 36 37 38-39 40 41-42 43 44-45 46 47-48 49 50 51
S1,S2 NC HPD1
Input
SDA1
SCL1 B11, A11
VCC
B12, A12 GND B13, A13 VCC B14, A14 VDD HPD2 SDA2
10/43
STDVE103A Table 2.
Pin number 52 53-54 55 56-57 58 59-60 61 62-63 64
Pin configuration Pin description (continued)
Pin name SCL2 B21, A21 VCC B22, A22 GND B23, A23 Type I/O Input, TMDS Function Port 2 DDC bus clock line Port 2 differential inputs for channel 1 Supply voltage (3.3 V 5%) Port 2 differential inputs for channel 2 Ground
Power
Input, TMDS Power
Input, TMDS Port 2 differential inputs for channel 3 Power Input, TMDS Supply voltage (3.3 V 5%) Port 2 differential inputs for channel 4 Port 3 hot plug detector output.
VCC
B24, A24 HPD3
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Functional description
STDVE103A
4
Functional description
The STDVE103A routes physical layer signals for high bandwidth digital video and is compatible with low voltage differential signaling standards such as the TMDS. The device passes the differential inputs from a video source to a common display when it is in the active mode of operation. The device conforms to the TMDS standard on both inputs and outputs. The low on-resistance and low I/O capacitance of the switch in STDVE103A result in a very small propagation delay. The device integrates SPDT-type switches for 3 differential data TMDS channels and 1 differential clock channel. Additionally, it integrates the switches for DDC and HPD line switching with I2C repeater on the DDC lines. The I2C interface of the selected input port is linked to the I2C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused ports, the I2C interfaces are isolated and the HPD pins are driven to L state.
4.1
Adaptive equalizer
The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation from long or lossy transmission media. The inputs present high impedance when the device is not active or when VCC is absent or 0 V. In all other cases, the 50 termination resistors on input channels are present. This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the gain stage of the equalizer to compensate the signal degradation and then the signals are driven on to the output ports. The equalizer is fully adaptive and automatic in function providing smaller gain at low frequencies and higher gain at high frequencies. The equalizer is optimized internally for an adaptive operation. Table 3. Gain frequency response
Frequency (MHz) 225 325 410 825 1650 Gain in dB 3 5 6.5 11 16
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STDVE103A Figure 6. STDVE103A gain vs. frequency
Functional description
The STDVE103A equalizer is fully adaptive and automatic in function. The equalizer's performance is optimized for all frequencies over the cable lenths from 1 m to 25 m.
Input termination
The STDVE103A integrates precise 50 5% termination resistors, pulled up to VCC, on all its differential input channels. External terminations are not required. This gives better performance and also minimizes the PCB board space. These on-chip termination resistors should match the differential characteristic impedance of the transmission line. Since the output driver consists of current steering devices, an output voltage is not generated without a termination resistor. Output voltage levels are dependent on the value of the total termination resistance. The STDVE103A produces TMDS output levels for point-to-point links that are doubly terminated (100 at each end). With the typical 10 mA output current, the STDVE103A produces an output voltage of 3.3 - 0.5 V = 2.8 V when driving a termination line terminated at each end. The input terminations are selectable thus saving power for the unselected ports.
Output buffers
Each differential output of the STDVE103A drives external 50 load (pull-up resistor) and conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential current-steering devices. The driver outputs are short-circuit current limited and are high-impedance to ground when S1, S2 = HL or the device is not powered. The current steering architecture requires a resistive load to terminate the signal to complete the transmission loop from VCC to GND through the termination resistor. Because the device switches the direction of the current flow and not voltage levels, the output voltage swing is determined by VCC minus the voltage drop across the termination resistor. The output current drivers are controlled by the S1, S2 pin and are turned off when S1, S2 is a HL. A stable 10 mA current is derived by accurate internal current mirrors of a stable reference current which is generated by band-gap voltage across the REXT. The differential output driver provides a typical 10 mA current sink capability, which provides a typical 500 mV voltage drop across a 50 termination resistor.
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Functional description
STDVE103A
TMDS voltage levels
The TMDS interface standard is a signaling method intended for point-to-point communication over a tightly controlled impedance medium. The TMDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The device is capable of detecting differential signals as low as 100 mV within the entire common mode voltage range.
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STDVE103A
Functional description
4.2
4.2.1
Operating modes
SEL operating modes
The active source is selected by configuring source select inputs, S1 and S2. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I2C interface of the selected input port is linked to the I2C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. Table 4. SEL operating modes
Control pins S2 S1 Y/Z A1/B1 terminations of A2/B2 and A3/B3 are disconnected A2/B2 terminations of A1/B1 and A3/B3 are disconnected A3/B3 terminations of A1/B1 and A2/B2 are disconnected None (Z). All terminations are disconnected I/O selected SCL_SINK SDA_SINK SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 None (Z) Are pulled high by external pullup termination Hot-plug detect status HPD1 HPD2 HPD3
H
H
HPD_SINK
L
L
H
L
L
HPD_SINK
L
L
L
L
L
HPD_SINK
L
H
L
L
L
H: logic high; L: logic low; X: don't care; Z: high impedance
4.3
HPD pins
The input pin HPD_SINK is 5 V tolerant, allowing direct connection to 5 V signals. The switch is able to pass both 0 V and 5 V signal levels. The HPD_SINK is an input pin while the HPD1, HPD2 and HPD3 are outputs.
4.4
DDC channels
The DDC channels are designed with a bi-directional NMOS gate, providing 5 V signal tolerance. The 5 V tolerance allows direct connection to a standard I2C bus, thus eliminating the need for a level shifter. There should be external pull-up resistors on either side of the device on both the SCL and SDA lines.
15/43
Functional description
STDVE103A
4.5
I2C DDC line repeater
The device contains two identical bi-directional open-drain, non-inverting buffer circuits that enable I2C DDC bus lines to be extended without degradation in system performance. The STDVE103A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I2C bus, while retaining all the operating modes and features of the I2C system. This enables two buses of 400 pF bus capacitance to be connected in an I2C application. These buffers are operational from a supply voltage of 3.0 to 3.6 V. The I2C bus capacitance limit of 400 pF restricts the number of devices and bus length. The STDVE103A enables the system designer to isolate the two halves of a bus, accommodating more I2C devices or longer trace lengths. It can also be used to run two buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is isolated when 400 kHz operation of the other bus is required. The STDVE103A can be used to run the I2C bus at both 5 V and 3.3 V interface levels. Two or more STDVE103As cannot be connected in series. The STDVE103A design does not allow this configuration. Since there is no direction pin, slightly different "legal" low voltage levels are used to avoid lock-up conditions between the input and output. A valid low applied at the input of STDVE103A is propagated as a buffered low with a slightly higher value on the enabled outputs. When this buffered low is applied to another STDVE103A in series, the second STDVE103A will not recognize it as a valid low and will not propagate it as a buffered low again. The S1 and S2 (SEL) lines act as control signals for the corresponding A, B or C ports. Note that the SEL line has an internal pull-down resistor. The SEL line should not change state during an I2C operation, because disabling during bus operation hangs the bus and enabling part way through a bus cycle could confuse the I2C parts being enabled. The SEL input should change state only when the global bus and the repeater port are in idle state, to prevent system failures. The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents a lock-up condition from occurring when the input low condition is released. As with the standard I2C system, pull up resistors are required to provide the logic high levels on the buffered bus. The STDVE103A has standard open collector configuration of the I2C bus. The size of the pull up resistors depends on the system, but each side of the repeater must have a pull up resistor. This part is designed to work with standard mode and fast mode I2C devices. Standard mode I2C devices only specify 3 mA output drive, this limits the termination current to 3 mA in a generic I2C system where standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used.
4.6
Power-down condition
The HL combination of S1, S2 is used to disable most of the internal circuitry of STDVE103A that puts the device in a low power mode of operation.
16/43
STDVE103A
Functional description
4.7
Bias
The bandgap reference voltage over the external REXT reference resistor sets the internal bias reference current. This current and its factors (achieved by employing highly accurate and well matched current mirror circuit topologies) are generated on-chip and used by several internal modules. The 10 mA current used by the transmitter block is also generated using this reference current. It is important to ensure that the REXT value is within the 1% tolerance range of its typical value. Table 5. Bias parameter
Min Typ 1.2 Max Unit V
Parameter Bandgap voltage
The output voltage swing depends on 3 components: supply voltage (Vsupply), termination resistor (RT) and current drive (Idrive). The supply voltage can vary from 3.3 V 5%, termination resistor can vary from 50 10%. The voltage on the output is given by:
V supply - I drive x R T
The variation on Idrive must be controlled to ensure that the voltage on HDMI output is within the HDMI specification under all conditions. This is achieved when:
400mV I drive x R T 600mV
with typical value centered at 500 mV.
4.8
Timing between HPD and DDC
It is important to ensure that the I2C DDC interface is ready by the time the HPD detection is complete. As soon as the discovery is finished by the HPD detection, the configuration data is exchanged between a source and sink through the I2C DDC interface. The STDVE003's DDC interface is ready for communication as soon as the power supply to the chip is present and stable. When the desired port is enabled and the chip is out of shutdown mode, the I2C DDC lines can be used for communication. Thus, as soon as the HPD detection sequence is complete, the DDC interface can be readily used. There is no delay between the HPD detection and I2C DDC interface to be ready.
17/43
Maximum rating
STDVE103A
5
Maximum rating
Stressing the device above the rating listed in the "absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Symbol
VCC VDD
Absolute maximum ratings
Parameter Supply voltage to ground Supply voltage to Ground (DDC, HPD, S1, S2) DC input voltage (TMDS ports) Value -0.5 to +4.0 -0.5 to +6.0 1.7 to +4.0 -0.5 to +6.0 120 -65 to +150 300 Human body model -5 to +5 V V mA C C kV Unit V
VI
SDA1, SCL1, SDA2, SCL2, SDA3, SCL3,SDA_SINK, SCL_SINK, HPD_SINK, HPD1, HPD2, HPD3, S1, S2 DC output current Storage temperature Lead temperature (10 sec) Electrostatic discharge voltage on all IOs
IO TSTG TL VESD
Table 7.
Symbol JA
Thermal data
Parameter Thermal coefficient (junction-ambient)
TQFP-64
Unit C/W
TBD
18/43
STDVE103A
Maximum rating
5.1 5.2
Recommended operating conditions DC electrical characteristics
TA = -40 to +85 C, VCC = 3.3 V 5% (a)
Table 8.
Symbol VCC VDD
Power supply characteristics
Value Parameter Supply voltage Supply voltage All inputs/outputs are enabled. Inputs are terminated with 50 to VCC.
VCC = 3.465 V
Test condition Min 3.135 4.5 Typ 3.3 5.0 Max 3.465 5.5
Unit V V
ICC
Supply current
300
mA
Data rate = 3.4 Gbps ICC IDD Supply current Supply current (VDD supply) S1, S2 = HL 2 20 5 mA mA
Table 9.
Symbol
DC specifications for TMDS differential inputs
Value Parameter Differential input high threshold (peak-to-peak) Differential input low threshold Differential input voltage (peak-to-peak)(1) Common mode voltage range Input capacitance IN+ or IN- to GND F = 1 MHz Test condition Min Typ 0 Max 150 mV Unit
VTH
VCC = 3.465 V over the entire VCMR VCC = 3.465 V over the entire VCMR VCC = 3.465 V -150
VTL
0
mV
VID
150
1560
mV
VCMR CIN
VCC - 0.3 3.5
VCC - 0.04
V pF
1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |.
a. Typical parameters are measured at VCC = 3.3 V, TA = +25 C.
19/43
Maximum rating Table 10.
Symbol
STDVE103A
DC specifications for TMDS differential ouputs
Value Parameter Single-ended high level output voltage Single-ended low level output voltage Single ended output swing voltage Differential output voltage (peak-to-peak)(1) Differential output high level current Differential output low level current Output driver shortcircuit current (continuous) OUT = GND through a 50 resistor. See Figure 11 OUT+ or OUTto GND when tristate F = 1 MHz VCC = 3.3 V RTERM = 50 VCC = 3.3 V RTERM = 50 Test condition Min Typ Max VCC+10 VCC-400 500 600 mV mV mV Unit
VOH VOL Vswing
VCC-10 VCC-600 400
VOD
800
1000
1200
mV
IOH IOL
0 8 10
50 12
A mA
|ISC|
12
mA
COUT
Output capacitance
5.5
pF
1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |
20/43
STDVE103A Table 11.
Symbol
Maximum rating
DC specifications for SEL (S1, S2) inputs
Value Parameter Test condition Min Typ Max V 0.8 -0.8 +5 +5 3.5 V V A A pF High level guaranteed Low level guaranteed VCC = 3.465 V IIN = -18 mA VCC = 3.465 V VIN = VCC VCC = 3.465 V VIN = GND Pin to GND F = 1 MHz Unit
VIH VIL VIK IIH IIL CIN
HIGH level input voltage LOW level input voltage Clamp diode voltage Input high current Input low current Input capacitance
2.0 -0.5 -1.2 -5 -5
Table 12.
Symbol
Input termination resistor
Parameter Differential input termination resistor on IN channels relative to VCC Test condition Value Unit
RTERM
IIN = -10 mA
45
50
55
Table 13.
Symbol
External reference resistor
Value Parameter Resistor for TMDS compliant voltage swing range Test condition Min Typ 4.7 Max K Unit
REXT
Tolerance for R = 1%
21/43
Maximum rating Table 14.
Symbol VI(DDC)
STDVE103A
DDC I/O pins (switch)
Value Parameter Input voltage VCC = 3.465 V A, B, C ports = 5.3 V Y port = 0.0 V Switch is isolated Test condition Min GND Typ Max 5.3 V Unit
6
A
II(leak)
Input leakage current VCC = 3.465 V A, B, C ports = 3.3 V Y port = 0.0 V Switch is isolated VI=0 V F = 1 MHz Switch disabled 5 2 A
pF
CI/O
Input/output capacitance VI=0 V F = 1 MHz Switch enabled 9 pF
Table 15.
Symbol
Status pins (HPD_SINK)
Value Parameter Test condition Min Typ Max 5.3 0.8 4 2 V V A A VCC = 3.3 V High level guaranteed VCC = 3.3 V Low level guaranteed VCC = 3.465 V Y = 5.3 V Unit
VIH VIL
High level input voltage Low level input voltage
2.0 GND
II(leak)
Input leakage current VCC = 3.465 V Y = 3.3 V
22/43
STDVE103A
Maximum rating
Table 16.
Symbol V
Status pins (HPD1, HPD2, HPD3)(1)
Value Parameter Voltage VI = 0 V F = 1 MHz Switch disabled Test condition Min GND 5 Typ Max 5.3 V pF Unit
CI/O
Input/output capacitance VI = 0 V F = 1 MHz Switch enabled Output low voltage (open drain I/Os) VCC = 3.3 V IOL = 8 mA 9 pF
VOL
0.4
V
1. Typical parameters are measured at VCC = 3.3 V, TA = +25 C.
23/43
Maximum rating
STDVE103A
5.3
Table 17.
Symbol
DC electrical characteristics (I2C repeater)
(TA = -40 to +85 C, VCC = 3.3 V 5%, GND = 0 V; unless otherwise specified) Supplies
Value Parameter Test condition Min VCC DC supply voltage 3.135 Typ 3.3 Max 3.465 V Unit
Table 18.
Symbol
Input/output SDA, SCL
Value Parameter High level input voltage Low level input voltage(1) Low level input voltage contention(1) Input clamp voltage Input current low (SDA, SCL) II = -18 mA Input current low (SDA, SCL) VI = 3.465 V (SDA, SCL) VI = 5.3 V (SDA, SCL) IOL = 3 mA IOL = 6 mA VO = 3.6 V; driver disabled VO = 5.3 V; driver disabled VI = 3 V or 0 V Test condition Min Typ Max 5.3 0.3 VCC 0.4 V V V V A A A V V A A pF Unit
VIH VIL VILc VIK IIL
0.7 VCC -0.5 -0.5
- - - -
- - - -
-1.2 1 10 10 0.4 0.65
IIH
Input current high (SDA, SCL)
VOL
LOW-level output voltage
IOH
Output high level leakage current
- - -
- -
6
10 10 7(2)
CI
Input capacitance
1. VIL specification is for the first low level seen by the SDA/SCL lines. VILc is for the second and subsequent low levels seen by the SDA/SCL lines. 2. The SCL/SDA CI is about 200 pF when VCC = 0 V. The STDVE103A should be used in applications where power is secured to the repeater but an active bus remains on either set of the SDA/SCL pins.
24/43
STDVE103A
Maximum rating
5.4
Dynamic switching characteristics(b)
TA = -40 to +85 C, VCC = 3.3 V 5%, RTERM = 50 5%, CL = 5 pF). Typical values are at TA = +25 C and VCC = 3.3 V.
Table 19.
Symbol
Clock and data rate
Value Parameter Clock frequency (1/10th of the differenttial data rate) Signaling rate Test condition Min Typ Max 340 3.4 MHz Gbps Unit
fCK Drate
25
Table 20.
Symbol
Equalizer gain
Value Parameter Test condition Min At 225 MHz Typ 10 15 Max dB dB Unit
G_EQ
Equalizer gain At 340 MHz
Table 21.
Symbol tr tf tPLH tPHL
Differential output timings
Value Parameter Differential data and clock output rise/fall times Differential low to high propagation delay Differential high to low propagation delay Test condition Min 20% to 80% of VOD 80% to 20% of VOD Alternating 1 and 0 pattern at slow and fast data rates Measure at 50% VOD between input to output 75 75 250 250 Typ 150 150 Max 240 240 800 800 ps ps ps ps Unit
b.
The timing values in this section are tested during characterization and are guaranteed by design and simulation. Not tested in production.
25/43
Maximum rating Table 22.
Symbol
STDVE103A
Skew times
Value Parameter Inter-pair channel-tochannel output skew Pulse skew Intra-pair differential skew Difference in propagation delay (tPLH or tPHL) among all output channels | tPLH - tPHL | 25 Test condition Min Typ Max 100 80 50 ps ps ps Unit
tSK(O) tSK(P) tSK(D)
tSK(CC)
Output channel to channel skew
50
125
ps
Table 23.
Symbol
Turn-on and turn-off times
Value Parameter Test condition Min TMDS output enable time Time from OE_N to OUT change from tristate to active Time from OE_N to OUT change from active to tristate Typ Max Unit
tON
12
20
ns
tOFF
TMDS output disable time
6
10
ns
Table 24.
Symbol
DDC I/O pins
Value Parameter Test condition Min Refer to Section 5.5 Typ Max Unit
Table 25.
Symbol
Status pins (HPD_SINK, HPD1, HPD2, HPD3, S1, S2)
Value Parameter Propagation delay (from Y_HPD to the active port of HPD) Test condition Min Typ 150 Max ns Unit
tPD(HPD)
CL = 10 pF, RPU = 1 K
TON/OFF
Switch time (from port select to the CL = 10 pF latest valid status of HPD)
50
ns
26/43
STDVE103A Table 26.
Symbol
Maximum rating
Jitter
Value Parameter Test condition Min Typ 35 Max ps (p-p) PRBS pattern at 1.6 Gbps (800 MHz) Unit
tJIT
Total jitter(1)
1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. Input differential voltage = VID = 500 mV, PRBS random pattern at 1.65 Gbps, tr=tf=50 ps (20% to 80%). Jitter parameter is not production-tested but guaranteed through characterization on a sample-to-sample basis.
27/43
Maximum rating
STDVE103A
5.5
Dynamic switching characteristics (I2C repeater)
TA = -40 to +85 C, VCC = 3.3 V 5%. Typical values are at TA = +25 C and VCC = 3.3 V. . I2C repeater(1)
Value Parameter Test condition Min Typ Max 100 400 kHz kHz Standard mode Fast mode 100 KHz See Figure 19 Voltage on line = 5V Cmax=400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions. Unit
Table 27.
Symbol
fSCL
I2C clock frequency
4.7
s
tLOW
Low duration on SCL pin
400 KHz See Figure 19 Voltage on line = 5V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions. 100 KHz See Figure 19 Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions.
1.3
s
4.7
s
tLOW
Low duration on SCL pin 400 KHz See Figure 19 Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions.
1.3
s
28/43
STDVE103A Table 27.
Symbol
Maximum rating
I2C repeater(1) (continued)
Value Parameter Test condition Min 100 KHz See Figure 19 Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions Typ Max Unit
4.0
s
tHIGH
High duration on SCL pin 400 KHz See Figure 19 Voltage on line = 5 V Cmax = 400 pF, Rmax=2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions 100 KHz Refer section 14.12, Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions
0.6
s
4.0
s
tHIGH
High duration on SCL pin 400 KHz See Figure 19 Voltage on line = 3.3 V, Cmax=400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20 % time intervals on both transitions 400 KHz Waveform 1 (Figure 17) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 400 KHz Waveform 1 (Figure 17) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 400 KHz Waveform 1 (Figure 17) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K
0.6
s
tPHL
Propagation delay
250
s
tPLH
Propagation delay
300
s
tPHL
Propagation delay
250
ns
29/43
Maximum rating Table 27.
Symbol
STDVE103A
I2C repeater(1) (continued)
Value Parameter Test condition Min 400 KHz Waveform 1 (Figure 17) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K 100 KHz Waveform 1 (Figure 17) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 100 KHz Waveform 1 (Figure 17) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 100 KHz Waveform 1 (Figure 17) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K 100 KHz Waveform 1 (Figure 17) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K 400 KHz Waveform 1 (Figure 17)(2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K Typ Max Unit
tPLH
Propagation delay
450
ns
tPHL
Propagation delay
250
ns
tPLH
Propagation delay
300
ns
tPHL
Propagation delay
250
ns
tPLH
Propagation delay
450
ns
300
ns
tf
Output fall time 400 KHz Waveform 1(2) Voltage on li ne = 3.3 V Cmax = 400pF, Rmax = 2 K 100 KHz Waveform 1 (Figure 17) (2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K 300 ns
300
ns
tf
Output fall time 100 KHz Waveform 1 (Figure 17)(2) Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K 300 ns
30/43
STDVE103A Table 27.
Symbol
Maximum rating
I2C repeater(1) (continued)
Value Parameter Test condition Min 400 KHz Waveform 1 (Figure 17)(2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K Typ Max Unit
300
ns
tr
Output rise time 400 KHz Waveform 1 (Figure 17)(2) Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K 100 KHz Waveform 1,(2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K 300 ns
1000
ns
tr
Output rise time 100 KHz Waveform 1 (Figure 17)(2) Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K 1000 ns
1. All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in production. 2. The tr transition time is specified with maximum load of 2 k pull-up resistance and 400 pF load capacitance. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times. Refer to Figure 9.
Table 28.
Symbol ESD (HBM)
ESD performance
Parameter All I/Os Test conditions Human body model Min Typ Max Unit kV
5
31/43
Maximum rating Figure 7. Test circuit for electrical characteristics
STDVE103A
VCC CL VOUT+
VIN+
Pulse generator
RT RT
VIN-
STDVE103A
VOUTCL
100
CS00065A
1. CL = load capacitance: include jig and probe capacitance. 2. RT = termination resistance; should be equal to ZOUT of the pulse generator.
Figure 8.
TMDS output driver
VCC
RT ZO = RT
RT
TMDS driver
ZO = RT
TMDS receiver
CS00069
1. ZO = characteristic impedance of the cable. 2. RT = termination resistance: should be equal to ZO of the cable. Both are equal to 50W.
32/43
STDVE103A Figure 9. Test circuit for HDMI receiver and driver
Maximum rating
VCC
RT A VID B
RT Y TMDS receiver TMDS driver CL = 0.5pF VY Z
RT
VA
VCC
VB
VID = VA - VB
VSwing = VY - VZ
VZ
RT
CS00071
1. RT = 50 .
33/43
Maximum rating Figure 10. Test circuit for turn off and turn off times
STDVE103A
10F
0.1 F 0.01F
1.15 V VIN+ 1.0 V
CL VCC
50 1.2 V
1.15 V VIN1.0 V
STDVE103A
50
SHDN_N CL GND 4.7 K1%
REXT Pulse generator 50
CS00072A
1. CL = 5 pF
Figure 11. Test circuit for short circuit output current
50 ISC TMDS driver 50
0V or 3.465 V
34/43
STDVE103A Figure 12. Propagation delays
VA VCC
Maximum rating
VCM
VID
VCM VCC - 0.4
VB
0.4V VID 0V
VID
VID(p-p)
-0.4V
tpLH 80%
VOD(O)
tpHL 100% 80% 0V Differential
VOD(p-p)
20% Output
20% 0% VOD(U)
tr
tf
Figure 13. Turn-on and turn-off times
SHDN_N 1.50 V 1.50 V 0V tOFF tON VOH VOUT+ when VID= +150mV VOUT- when VID= -150mV 50% 50% 1.2 V tOFF tON 1.2 V VOUT+ when VID= -150mV VOUT- when VID= +150mV 50% 50% VOL 3.0 V
35/43
Maximum rating Figure 14. TSK(O)
STDVE103A
3.5V
2.5V
Data In
1.5V tpLHX tpHLX
VOH
2.5V 2.5V
Data Out at Port 0 VOL tSK(o) VOH
2.5V
Data Out at Port 1 VOL tpLHY tpHLY
tSK(o) = | tpLHy - tpLHx | or | tpHLy - tpHLx |
Figure 15. TSK(P)
Figure 16. TSK(D)
36/43
STDVE103A Figure 17. AC waveform 1 (I2C lines)
Maximum rating
Figure 18. Test circuit for AC measurements (I2C lines)
Figure 19. I2C bus timing
37/43
Application information
STDVE103A
6
6.1
Application information
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is recommended to always apply VCC before applying any signals to the input/output or control pins.
6.2
Power supply requirements
Bypass each of the VCC pins with 0.1 F and 1 nF capacitors in parallel as close to the device as possible, with the smaller-valued capacitor as close to the VCC pin of the device as possible. All VCC pins can be tied to a single 3.3 V power source. A 0.01 F capacitor is connected from each VCC pin directly to ground to filter supply noise. The maximum power supply variation can only be 5% as per the HDMI specifications. The maximum tolerable noise ripple on 3.3 V supply must be within a specified limit.
6.3
Differential traces
The high-speed TMDS inputs are the most critical parts for the device. There are several considera-tions to minimize discontinuities on these transmission lines between the connectors and the device. (a) Maintain 100- differential transmission line impedance into and out of the STDVE103A. (b) Keep an uninterrupted ground plane below the high-speed I/Os. (c) Keep the ground-path vias to the device as close as possible to allow the shortest return current path. (d) Layout of the TMDS differential inputs should be with the shortest stubs from the connectors. Output trace characteristics affect the performance of the STDVE103A. Use controlled impedance traces to match trace impedance to both the transmission medium impedance and termination resistor. Run the differential traces close together to minimize the effects of the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to further prevent impedance discontinuities.
38/43
STDVE103A
Application information
6.3.1
I2C lines application information
A typical application is shown in the figure below. In the example, the system master is running on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz unless the slave bus is isolated and then the master bus can run at 400 kHz. Master devices can be placed on either bus. Figure 20. Typical application of I2C bus system
3.3V 5.0V
SDA SCL Bus Master 400 kHz SHDN_N
SDA
SDA
SDA SCL Slave 100 kHz
SCL SCL STDVE103A SEL
BUS 0
BUS 1
AM00712V1
The STDVE103A DDC lines are 5 V tolerant; so it does not require any extra circuitry to translate between the different bus voltages.
39/43
Package mechanical data
STDVE103A
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 21. TQFP64 package outline
A
D D1 D3
48 33
A2 A1
0.10mm
49
32
.004 Seating Plane
E3
E1
17
L
64
L1
E
K
1
e
16
B
C
0051434/E
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STDVE103A Table 29. TQFP64 mechanical data
Millimeters Symbol Min A A1 A2 b c D D1 D3 E E1 E3 e L L1 K 0 0.45 11.80 9.80 0.05 0.95 0.17 0.09 11.80 9.80 0.10 1 0.22 0.15 12 10 7.50 12 10 7.50 0.50 0.60 Typ
Package mechanical data
Max 1.20 0.15 1.05 0.27 0.20 12.20 10.20
12.20 10.20
0.75
1
7
Figure 22. TQFP64 tape and reel information
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Revision history
STDVE103A
8
Revision history
Table 30.
Date 21-Jul-2008
Document revision history
Revision 1 Initial release. Changes
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STDVE103A
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